A cache system comprising a cache tag buffer 270 for storing a part of a
cache tag memory 260. When a memory processing request is issued from a
processor 10, a cache control means 280 retrieves both of the cache tag
memory 260 and the cache tag buffer 270. If a target cache block is
present in the cache tag buffer 270, then, without waiting for a retrieval
result of the cache tag memory 260, the cache control circuit 280 accesses
the cache data memory 250 using information of the cache block.
