Circuits for adjusting the duty cycle of a clock(s) signal include a
negative feedback loop for applying an offset signal to the uncorrected
clock signal(s). The offset signal, which corresponds to a duty cycle
error of the corrected clock signal(s), adjusts the slicing level of the
uncorrected clock signal(s) to cause the duty cycle error to converge
toward a predetermined value, for example, zero. The techniques may be
used to adjust the duty cycle error of differential clock signals as well
as single-ended clock signals.
