A system includes a digital phase lock loop (PLL) constructed from an all
digital circuit implementation and standard cell construction. The digital
PLL includes a digital frequency synthesizer and a digital phase detector.
The digital frequency synthesizer includes a digital DLL including a
plurality of delay chains, each of the delay chains including at least one
digitally programmable delay element for configuring the plurality of
delay chains to achieve a phase lock with an input reference signal. The
digital frequency synthesizer also a non-glitching MUX electrically
coupled to the digital DLL for selecting a tap output from one of the at
least one digitally programmable delay element to select at least one
pulse glitch-free from the selected output tap, and a phase accumulator
electrically coupled to the non-glitching MUX for precisely dividing a
timing period of the input reference signal and for selecting a tap output
from one of the at least one digitally programmable delay element to
select at least one pulse at a precise point in the timing period from the
output tap. The digital phase detector, is electrically coupled to the
digital frequency synthesizer to compare an edge of the input reference
signal to an edge of a synthesized signal to provide a digital code
information representing a phase error between the edge of the input
reference signal and the edge of the synthesized signal.
