A method of testing integrated circuits for the effect of NBTI degradation.
A static DC stress voltage is applied to the voltage supply input of the
circuit. This circuit is held at this voltage for a given stress period.
The application of the DC voltage is equivalent to applying a negative
gate bias, and isolates the effects of NBTI degradation from CHC (channel
hot carrier) degradation or other degradation that occurs when the circuit
has a clocked input.
