Nonvolatile semiconductor memory

   
   

One sub-data circuit is disposed for one selected bit line in a 4-level memory. The sub-data circuit has first and second latch circuits for serial accessing. In reading, an upper bit is latched through a sense latch in the first latch circuit. A reading operation of a lower bit is controlled to a value of the upper bit latched in the first latch circuit. In programming, an upper bit is latched in the first latch circuit. A program operation of a lower bit is controlled to a value of the upper bit latched in the first latch circuit.

 
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