In a recordable disk recording controller circuit, a data buffer manager
receives a command and sends the command to a micro-controller. The
micro-controller generates a set of register batches from each command and
sends the register data and index of the register batch to a batch
register controller. The batch register controller receives the register
data and index of the register batch from the micro-controller and stores
the received register data and index of the register batch in a batch
buffer. The batch register controller retrieves the register batches from
the batch buffer and writes the master registers of an encoder controller
based on the register index and register data of the register batches
after the master registers of the encoder controller are updated into the
slave registers of the encoder controller. The encoder controller
generates control signals to a recording circuit depending on updated
slave registers. Such control signals cause the recording circuit to
record a signal representative of signal data on a recordable disk located
in a recordable disk driver.
