Implementation of wavelet functions in hardware

   
   

An architecture component for use in performing a wavelet transform of a sampled signal, and an architecture including such components are disclosed. The architecture component includes a multiplier, and a multiplexor to multiplex a number n of filter coefficients onto the multiplier. The multiplier processes n consecutive samples with consecutive coefficients, successive multiplier outputs being stored for subsequent processing to generate an output of the filter after every n samples. The wavelet transform may be a discrete wavelet transform or a wavelet packet decomposition. The architecture component may be configured to multiplex two or more coefficients onto a multiplier. Embodiments are disclosed in which the components are derived from a parameterized description in a hardware description language.

 
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