A data processor which includes a first processor for executing a first
instruction set and a second processor for executing a second instruction
set different from the first instruction set. When the first processor
executes a predetermined instruction of the first instruction set the
second processor executes an instruction of the second instructions set.
The first processor may be a reduced instruction set computer (RISC) type
processor, the second processor may be a very long instruction word (VLIW)
type processor, the first instruction set may be a RISC instruction set
and the second instruction set may be a VLIW instruction set. The
predetermined instruction of the RISC instruction set executed by the
first processor may be a branch instruction causing a branch to a specific
address space at which VLIW instructions are stored. Thereafter, the VLIW
instructions at the specific address space are executed by the VLIW type
processor.
