Memory region based data pre-fetching

   
   

As microprocessor speeds increase, performance is more affected by data access operations. A combined solution of hardware and software directed pre-fetching limits additional instructions in a program stream, and minimizes additional hardware resources. In the current invention, the hardware and software directed pre-fetching technique is performed without explicit pre-fetch instructions utilized within the program stream and occupies a minimal amount of additional chip area. To minimize instruction bandwidth of the processor, the software and hardware directed pre-fetching approach uses additional registers located at an architectural level of the processor to specify pre-fetch regions, and a respective stride used for each of the regions. The impact to the instruction bandwidth of processing of instructions by the processor is limited to those additional instructions contained within the application that are required to set these registers. The frequency of pre-fetches is controlled using a spacing of memory access instructions contained within the application.

Mientras que las velocidades del microprocesador aumentan, el funcionamiento es afectado más por operaciones del acceso de los datos. Una solución combinada del hardware y de pre-traer dirigido software limita instrucciones adicionales en una corriente del programa, y reduce al mínimo recursos de hardware adicionales. En la invención actual, el hardware y el software técnica pre-que trae dirigida se realiza sin las instrucciones explícitas del pre-fetch utilizadas dentro de la corriente del programa y ocupa una cantidad mínima de área adicional de la viruta. Para reducir al mínimo la anchura de banda de la instrucción del procesador, el software y el hardware ordenaron pre-traer a aplicaciones del acercamiento los registros adicionales situados en un nivel arquitectónico del procesador para especificar regiones del pre-fetch, y un paso grande respectivo usado para cada uno de las regiones. El impacto a la anchura de banda de la instrucción del proceso de instrucciones por el procesador se limita a esas instrucciones adicionales contenidas dentro del uso que se requieran para fijar estos registros. La frecuencia de pre-fetches es controlada con un espaciamiento de las instrucciones de acceso de memoria contenidas dentro del uso.

 
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