High-speed programmable synchronous counter for use in a phase locked loop

   
   

A high-speed programmable synchronous counter is disclosed. The high speed counter includes a most-significant-bit counter synchronized with a least-significant bit counter. The least-significant-bit counter is programmed to an initial state and configured to decrement a state with each pulse of a clock wave. The least-significant-bit counter provides an output signal when the least-significant-bit counter has a zero-count state. The most-significant-bit counter decrements when the least-significant-bit counter has a zero-count state and provides an output signal when the least-significant-bit counter has a zero-count state. A counter output pulse is generated and the high-speed counter is reset to the initial state when both the least-significant bit counter and the most-significant bit counter have a zero-count state.

 
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