An apparatus and method for providing a high speed linear feedback shift register is disclosed. The high speed linear feedback shift register of the present invention comprises multiplexer flip flop circuits. The multiplexer gate on the input of each flip flop circuit is the only gate between each pair of flip flop circuits of the present invention. The linear feedback shift register of the present invention is capable of operating as a counter that does not need to be reset. The linear feedback shift register of the present invention may be used as a clock divider circuit.

 
Web www.patentalert.com

< Circuit for reading memory elements

< Low-latency circuit for synchronizing data transfers between clock domains derived from a common clock

> Method of designing an integrated circuit memory architecture

> Charge pump using dynamic charge balance compensation circuit and method of operation
~ 00092