There is disclosed an apparatus for loading instructions into the instruction execution pipeline of a pipelined processor. The apparatus for loading instructions comprises: 1) an instruction loading circuit that loads instructions from a first instruction thread into the instruction execution pipeline; and 2) a branch instruction detection circuit that detects a branch instruction in the first instruction thread. In response to the branch instruction detection, the instruction loading circuit stops loading instructions from the first instruction thread into the instruction execution pipeline and begins loading instructions from a second instruction thread into the instruction execution pipeline.