A semiconductor integrated circuit includes a control data storage circuit (6) having nonvolatile storage devices with programmed control data and a latch circuit for holding data read out from the storage devices, and a read control circuit (7) for controlling read operations of the control data, which are built in a semiconductor chip. The control data storage circuit (6) is divided into groups (1, 2), and the read control circuit (7) generates read control signals for the groups (1, 2) at different timings, using an output of an internal potential detecting circuit 41 as the timing reference, thereby preventing the peak of power consumption from unacceptably rising during reading operations.

 
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> Output buffer having a plurality of switching devices being turned on successively at shorter time intervals to achieve increasing drive capability using a predriver

> Arbitration method and circuit for control of integrated circuit double data rate (DDR) memory device output first-in, first-out (FIFO) registers

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