The present invention provides for a method and an apparatus for using a latency time period as a control input parameter. A manufacturing run of semiconductor devices is processed. Metrology data from the processed semiconductor devices is acquired. A latency analysis process is performed using the acquired metrology data. A feedback/feed-forward modification process is performed in response to the latency analysis process.

 
Web www.patentalert.com

< Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)

> Method and apparatus connecting between a fiber channel and a cache memory

~ 00072