A memory architecture uses shared sense amplifiers (18-23) and a centralized cache (26-29) that contains M bits. The memory architecture also includes a global bus (31) connecting the sense amplifiers and the centralized cache. The global bus includes n bits, and n Les utilisations d'une architecture de mémoire ont partagé les amplificateurs de sens (18-23) et une cachette centralisée (26-29) qui contient le peu de M. L'architecture de mémoire inclut également un autobus global (31) reliant les amplificateurs de sens et la cachette centralisée. L'autobus global inclut le peu de n, et le n

 
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