The present invention selects parts of an integrated circuit description for resynthesis and then prepares those parts for resynthesis. Initially, a resynthesis goal is input, with the resynthesis goal having been selected from a set of possible resynthesis goals. Plural buffer and/or logic trees in the integrated circuit description are then selected based on the resynthesis goal, and information for each of the selected trees is obtained and stored. The tree information includes: (i) a description of each tree cell, including cell types, cell coordinates, and flips and angles of the tree cell, (ii) a description of each input net, (iii) a signal arrival time for each input net as a function of a capacity of such input net, (iv) coordinates of each pin driving each input net, and (v) a maximum capacity of each input net that will prevent such input net from having a timing violation.