A low-cost, novel electrically erasable programmable read only memory cell embedded on core complementary metal oxide silicon for analog applications. The EEPROM memory cell includes a first well of P-type conductivity. An N-well coupler region is formed within the first well of P-type conductivity. An N-well window region is formed within the first well of P-type conductivity and spaced apart from the N-well coupler region. A first P+type region formed within the N-well window region. A second P+type region formed within the N-well window region and spaced apart from the first P+type region. A first contact is used to couple a first bit line to the first P+type region. A second contact which is used to couple a second bit line to the second P+type region. A single polysilicon layer is disposed over the N-well coupler region and the N-well window region. This single polysilicon layer defines a floating gate of the electrically erasable programmable read only memory cell.