The wafer inspection device carries out inspection of a plurality of integrated circuits provided with a plurality of electrode pads, respectively, in a condition where the integrated circuits are formed on a wafer. The wafer inspection device is provided with a test head for outputting a test pattern from a plurality of tester pogo pins, a test board to which the tester pogo pins are connected, and a substrate. A plurality of contact pins that correspond to the tester pogo pins, respectively, and are arranged in a matrix form are provided on the test board. A plurality of first terminals, which are connected, respectively, to the plurality of electrode pads, are provided on a first main surface of the substrate. A plurality of second terminals, which comprise terminal groups for each integrated circuit, are provided on a second main surface of the substrate. The terminal groups are arranged in a matrix form, and the second terminals are connected to the contact pins for each terminal group. Furthermore, inner wiring that connects the first and second terminals is provided in the substrate.