A method and apparatus for improved double buffering within a computing
system begins when a series of data blocks are received from a central
processing unit at a rate independent of a processing rate of a recipient
engine. For example, a video graphics circuit receives a series of data
blocks representing video frames from the central processing unit at a
rate independent of the refresh rate of the display. As the data blocks
are received, the video graphics circuit queues commands of the data
blocks. Typically, the commands include processing commands and a
processing rate synchronize command. To process the data blocks, the
co-processor pulls commands from the queued list and processes them to
produce recipient data. As the co-processor is producing the recipient
data, it is utilizing a first buffer. The co-processor continues to
process the commands and storing the results into the first buffer until
the processing rate synchronize command is detected. At this point, the
co-processor pauses processing of the commands. At the beginning of the
next cycle of the processing rate, the recipient data is provided from the
first buffer to the recipient engine and the co-processor resumes
processing of commands, which relate to another data block. As the
co-processor is processing the commands of the second data block, it is
utilizing a second buffer to store the processed data, i.e., the second
recipient data.