High resolution image data is stored in multiple frame buffers to enable the image data to be coupled to multiple lower resolution video streams. Despite physical address discontinuities at frame buffer crossover boundaries, addressing of the multiple frame buffers as a single logical frame buffer is made possible by first dividing the image data into pages using a page size appropriate for both the video mode and arrangement of the physical frame buffers within the high resolution image. Then a pitch is determined for each of the physical frame buffers that enables the alignment of the memory pages at the frame buffer crossovers. Then for video modes utilizing multiple bytes per pixel, the collection of bytes representing the pixels are aligned on the page boundaries at the frame buffer crossovers. Then linear address space is reserved for storing a single high resolution frame buffer. Then address translation hardware is configured to shuffle the mapping of the pages such that the pages within the reserved linear address space are routed to the appropriate pages within the multiple physical frame buffers to create a single high resolution frame buffer when accessed with an appropriate logical pitch.