A computer system including a first multiprocessor system connected to a
system bus and adapted to forward first and second load requests to the
system bus where the first load request precedes the second load request.
The system further includes a second multiprocessor system connected to
the system bus. The second multiprocessor system includes a memory
subsystem comprised of first and second cache levels arranged such that an
operation that retrieves data from the first cache level is arbitrated
through the second cache level before the data becomes available to the
system bus. A snoop control state machine of the second multiprocessor
system is adapted to stall arbitration of a second operation initiated in
the second cache level responsive to the second load request until a first
operation initiated in the first cache level responsive to the first load
request has been arbitrated through the second cache level. In other
words, new operations to a lower cache level are stalled until older
operations pass the common arbitration point. The second multiprocessor is
preferably adapted to send a data ready signal to the first multiprocessor
when data associated with the first load request is available for
transmission over the system bus.