A method of fabricating an MRAM cell includes providing an isolation transistor on a semiconductor substrate and forming an interconnect stack on the substrate in communication with one terminal of the transistor. A via is formed on the upper end of the stack so as to extend from a position below the digit line to a position above the digit line. The via also extends above the upper surface of a dielectric layer to provide an alignment key. A MTJ memory cell is positioned on the upper surface in contact with the via, and the ends of a free layer of magnetic material are spaced from the ends of a pinned edge of magnetic material by using sidewall spacers and selective etching.