A method of and system for determining calibration offsets to account for delays introduced "downstream" of the reference driver (24) of a tester system (18) to test electronic components such as SRAM semiconductor memory devices. Such delays are created by, among other elements, receiver channels (30) of the tester system. A plurality of calibration modules (100) are provided, one for each receiver channel. Each calibration modules has a transmission line (110) with a known delay, a first contact 102' and a second contact 102". The tester system includes a socket (52) having a plurality of contactors (54) for contacting the reference clock contact and data output contacts of the electronic components undergoing test. The first contact of each calibration module is positioned to engage the contactor that engages the reference clock contact of the electronic component. The second contact of each calibration module is positioned to engage a contactor that is different than the contactors that the second contacts of other calibration modules engage. Calibration offsets arising from delays introduced "downstream" of the tester system driver are determined for each receiver channel by subtracting the known delay for a calibration module associated with the receiver channel from the time between when (i) a test signal is provided by the reference driver at t.sub.0 and (ii) when the test signal is received at the receiver channel.