Magnetic tunnel junction random access memory architecture in which an
array of memory cells is arranged in rows and columns and each memory cell
includes a magnetic tunnel junction and a control transistor connected in
parallel. A control line is connected to the gate of each control
transistor in a row of control transistors and a metal programming line
extending adjacent to each magnetic tunnel junction is connected to the
control line in spaced apart intervals by vias. Further, groups of memory
cells in each column are connected in series to form local bit lines which
are connected in parallel to global bit lines. The series-parallel
configuration is read using a centrally located column to provide a
reference signal and data from columns on each side of the reference
column is compared to the reference signal or two columns in proximity are
differentially compared.