A floating point unit 26 is provided with a register bank 38 comprising 32
registers that may be used as either vector registers V or scalar
registers S. Data values are transferred between memory 30 and the
registers within the register bank 38 using contiguous block memory access
instructions. Vector processing instructions specify a sequence of
processing operations to be performed upon data values within a sequence
of registers. The register address is incremented between each operation
by an amount controlled by a stride value. Accordingly, the register
address can be incremented by values such as 0, 1, 2 or 4 between each
iteration. This provides a mechanism for retaining block memory access
instructions to contiguous memory addresses whilst supporting vector
matrix and/or complex operations in which the data values needed for each
iteration are not adjacent to one another in the memory 30.