An information processing system includes at least two processors sharing a common instruction set and address space. One processor at a time is active and executes program instructions. The active processor is placed into a sleep mode in which a current machine state is saved in the shared address space and instruction execution is suspended. A different processor becomes active and resumes instruction execution using the previously saved current machine state. The sleep mode is used to effectively pass control from one processor to another. In a specific embodiment, the currently active processor will resume operation after a sleep mode unless the user overrides that default selection. In another specific embodiment, the currently active processor selects which processor will become active following a sleep mode transition. In another specific embodiment, different processors share a common instruction set but each has additional unique characteristics, and the currently active processor selects a processor having characteristics matching the requirements of a specific phase of a computational process. In another specific embodiment, a notebook computer has two processors, one being very low-powered for extending battery life, the other being very fast for multimedia presentations and heavy number crunching. A user selects a processor appropriate for the intended use.